1. Field of the Invention
The present invention relates to a method for programming a fast-programmable Flash EEPROM (Electrically Erasable Programmable Read-Only Memory) cell, or array of such cells, that rely on the Source-Side Injection (SSI) mechanism for programming. The method is particularly well suited for low-power applications. The invention also relates to a novel low-voltage erase scheme of a fast-programmable Flash EEPROM cell or an array of such cells.
2. The Prior Art
Presently, most Flash memories use Channel Hot Electron Injection (CHEI) at the drain side of the memory cell, or Fowler-Nordheim Tunneling (FNT) for programming. The CHEI mechanism provides a relatively high programming speed (.about.10 .mu.s) at the expense of a high power consumption (.about.1 mA/bit) which limits the number of cells that can be programmed simultaneously (so-called page-mode programming) to a maximum of 8 bytes (Y. Miyawaki et al., IEEE J. Solid-State Circuits, vol.27, p.583, 1992). Furthermore, in order to allow a further scaling of the transistor dimensions towards 0.5 .mu.m and below, supply voltage scaling from 5V towards 3.3V and below also becomes mandatory. This supply voltage scaling is known to cause considerable degradation of the CHEI efficiency as well as the corresponding programming speed because the high power needed to trigger the CHEI can not be easily supplied on-chip from a high voltage generator or charge pumping circuit. Such additional circuitry increases the complexity and expense of the device.
On the other hand, FNT tunneling provides slower programming times (.about.100 .mu.s), but requires a lower power consumption so as to allow larger pages (.about.4 kbit). This reduces the effective programming time to 1 .mu.s/byte (T. Tanaka et al., IEEE J. Solid-State Circuits, vol.29, p.1366, 1994). Further improvements are hindered, however, by tunnel-oxide scaling limits and by the very high voltages (.about.18V) needed on chip for FNT, both compromising device reliability and process scalability.
The recent success of SSI as a viable alternative over FNT and CHEI for Flash programming is mainly due to its unique combination of moderate-to-low power consumption with very high programming speed at moderate voltages. A typical example of such a device relying on SSI for programming is the Applicant's High Injection Metal-Oxide-Semiconductor or HIMOS memory cell (J. Van Houdt et al., 11.sup.th IEEE Nonvolatile Semiconductor Memory Workshop, Feb. 1991; J. Van Houdt et al., IEEE Trans. Electron Devices, vol.ED-40, p.2255, 1993; J. Van Houdt et al., EP501941, published September 1992). As also described in the co-pending application Ser. Nos. 08/275,016 and 08/080,225, incorporated herein by reference, a speed-optimized implementation of the HIMOS (High Injection MOS) cell in a 0.7-.mu.m CMOS technology exhibits a 400 nanoseconds programming time while consuming only a moderate current (.about.35 .mu.A/cell) from a 5V supply. This result can be obtained by biasing the device at the maximum gate current, i.e. at a control-gate (CG) voltage (V.sub.cg) of 1.5V. The corresponding cell area is in the order of 15 .mu.m.sup.2 for a 0.7-.mu.m embedded Flash memory technology when implemented in a contactless virtual ground array as described in co-pending application Ser. No. 08/426,685. However, due to the growing demand for higher densities, and also in embedded memory applications like, for example, smart-cards, a continuous increase in array density and the scaling of the supply voltage will become desirable, if not mandatory. This evolution increases the relative impact of bitline voltage drops, and increases the importance of power consumption during programming.
Other references to SSI devices are listed below:
U.S. Pat. No. 5,338,952, issued Aug. 16, 1994, to Y. Yamauchi PA0 U.S. Pat. No. 5,394,360, issued Feb. 28, 1995, to T. Fukumoto PA0 U.S. Pat. No. 5,280,446, issued Jan. 18, 1994, to Y. Y. Ma et al. PA0 U.S. Pat. No. 5,408,115, issued Apr. 18, 1995, to K. T. Chang PA0 U.S. Pat. No. 5,284,784, issued Feb. 8, 1994, to M. H. Manley PA0 U.S. Pat. No. 5,029,130, issued Jul. 2, 1991, to B. Yeh
In contrast to Applicant's device as described in the co-pending applications Ser. Nos. 08/275,016 and 08/080,225, all these patents describe SSI devices and/or arrays that require complicated processing technologies (Yamauchi, Fukumoto, Ma and Manley use 3 polysilicon layers, while Chang and Yeh use special dielectrics) which presently are cost-effective only for very high-density stand-alone memories. Moreover, the corresponding devices described in the above-mentioned patents aim at maximizing the gate injection current in order to obtain the highest possible programming speed. This is typically done by biasing the select gate at a voltage slightly higher than the threshold voltage of this select channel. For the Applicant's device, as described in U.S. applications Ser. Nos. 08/275,016, 08/080,225 and 08/426,685, the select gate is referred to as Control Gate, and although the function is identical during programming, this select gate is given several names depending on the specific device, as indicated parenthetically in the following discussion. Yamauchi's patent mentions a cell current of 10 .mu.A for a select gate voltage of 2V (Auxiliary Gate, see FIG. 4). Fukumoto mentions a voltage of 1.5V to be applied to the select gate (Third Gate Electrode or Selection Gate, see col.3, line 39). Ma et al. mention a select gate voltage between 1.5 and 2V (Select Gate 47 in FIG. 4) which corresponds to a cell current of 20 .mu.A (col.9, line 22). More specifically, it is stated in the corresponding paper by Ma et al. (Symposium on VLSI Technology Digest of Technical Papers, p.49, 1994) that "maximum programmed threshold happens at V.sub.sg of 0.6V above Vt(SG)" (col. 2, 1.sup.st paragraph), where Vt(SG) represents the threshold voltage of the Select Gate SG. This implies that the `optimum` value for the select gate voltage is 1.8V (see table 1 in the same paper). Similarly, another publication on the same device (Symposium on VLSI Circuits Digest of Technical Papers, p.77, 1995) mentions that "a low wordline voltage of 1.8V is used during programming to maximize the hot electron injection rate" (col. 2, 3.sup.rd paragraph). Chang mentions a typical select gate voltage of between 1 and 2V which corresponds to a cell current in the range of 10-15 .mu.A (Select Gate 14 in FIG. 1a), while Manley prefers a select gate voltage of 1.5V or "a potential just above the threshold voltage of the select transistor (select gate 20 in FIG. 11), since this is the optimum condition for hot-electron injection . . . " (col.4, lines 22-24). Finally, Yeh reports that "a positive voltage level in the vicinity of the threshold voltage of the MOS structure defined by the control gate 29 (on the order of approximately 1 Volt), is applied to the control gate 29" (col.3, lines 46-49).
Thus, all above-mentioned patents mention a select-gate voltage between 1 and 2V, which corresponds to the maximum gate current, and, hence, maximum programming speed. Since for state-of-the-art MOS technologies the threshold voltage of the select channel is definitely smaller than 1V (typically 0.7V for a 0.7-.mu.m technology), all above-mentioned patents still describe a programming scheme which is essentially in the strong inversion or on-state of the MOS structure. This has the advantage that the maximum gate current (and thus the maximum threshold-voltage shift) is obtained and that the gate current is less sensitive to small variations in the select gate voltage (see e.g. the co-pending U.S. application Ser. Nos. 08/275,016 and 08/080,225, FIG. 4, or U.S. Pat. No. 5,338,952, issued Aug. 16, 1994, to Y. Yamauchi, FIG. 4).
Although in this case the programming cell current is only in the range of 10-50 .mu.A, a further reduction of this parameter will greatly improve the conditions for page-mode application and for supply voltage scaling. Indeed, if the supply voltage is scaled towards 3.3V, the injection efficiency may be increased by increasing the bitline voltage internally on-chip, as already suggested in the co-pending application Ser. Nos. 08/275,016 and 08/080,225, p.17, lines 4-13, and also in U.S. Pat. No. 5,280,446, col.9, lines 19-25. The power that can be delivered from such an on-chip high voltage generator or charge pump is, however, known to be limited in the order of a few .mu.A's (see e.g. U.S. Pat. No. 5,042,009, issued on Aug. 20, 1991, to R. Kazerounian et al.). It is, therefore, still not straightforward to increase the drain voltage internally on-chip for the devices reported in the prior art.
On the other hand, programming a larger number of cells simultaneously (page-mode programming) can reduce the effective programming time per bit considerably. However, the simultaneous programming of, for example, 1024 cells on a common wordline would again require 10-50 mA in the prior art devices, which is unacceptable from the point of view of power consumption and bitline voltage drops, especially if at the same time the drain voltage is to be increased internally on-chip for higher speed performance.
In the present application, these problems are solved and additional interesting features are demonstrated by optimizing the programming operation from the point of view of power consumption and page-mode programming speed, in contrast to the prior art which shows optimum solutions only from the point of view of programming speed per cell.